summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/lynxpoint/early_pch.c
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2023-04-20 14:25:13 +0200
committerFelix Held <felix-coreboot@felixheld.de>2024-08-15 21:42:32 +0000
commit1c25c63c78512916bb61c693be64dcc78c2ee72e (patch)
tree7925ef6991f1eff3e119b89c058c1945af0cb387 /src/southbridge/intel/lynxpoint/early_pch.c
parentc6889816d8ae8c0f15b7707820e6c40c311d5393 (diff)
include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
Both AGESA.h and cpu/amd/mtrr.h defined TOP_MEM and TOP_MEM2, but since it was defined as unsigned long in AGESA.h, a workaround was needed in cpu/amd/mtrr.h to not have the build fail due to a non-identical redefinition of TOP_MEM and TOP_MEM2. Just removing the workaround without reaming the defines isn't trivially possible, since the stoneyridge romstage.c still ends up including both definitions which can't be easily worked around. Now all non-vendorcode coreboot code uses TOP_MEM_MSR and TOP_MEM2_MSR while the vendorcode part uses TOP_MEM and TOP_MEM2 to avoid this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_pch.c')
0 files changed, 0 insertions, 0 deletions