diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-11-02 09:16:46 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 06:26:42 +0100 |
| commit | 9aa031e47157e37e8f3cd80cbc80215e2843eaa9 (patch) | |
| tree | 00df9615618ba326c925af63817c8f5c1e5cfb98 /src/southbridge/intel/lynxpoint/early_me.c | |
| parent | dc278f8fd0318caf0c11330478dff8453bb1107d (diff) | |
lynxpoint: Management Engine Updates
The ME9 requirements have added some registers and changed some
of the MBP state machine. Implement the changes found so far in
the ME9 BWG. There were a couple of reigster renames, but the
majority of th churn in the me.h header file is just introducing
the data structures in the same order as the ME9 BWG.
Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18
Signed-Off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2620
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_me.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_me.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 5b266cc10c..1eb30a1ff7 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -56,12 +56,12 @@ static inline void pci_write_dword_ptr(void *ptr, int offset) void intel_early_me_status(void) { struct me_hfs hfs; - struct me_gmes gmes; + struct me_hfs2 hfs2; pci_read_dword_ptr(&hfs, PCI_ME_HFS); - pci_read_dword_ptr(&gmes, PCI_ME_GMES); + pci_read_dword_ptr(&hfs2, PCI_ME_HFS2); - intel_me_status(&hfs, &gmes); + intel_me_status(&hfs, &hfs2); } int intel_early_me_init(void) @@ -73,6 +73,7 @@ int intel_early_me_init(void) printk(BIOS_INFO, "Intel ME early init\n"); /* Wait for ME UMA SIZE VALID bit to be set */ + /* FIXME: ME9 BGW indicates a 5 sec poll timeout. */ for (count = ME_RETRY; count > 0; --count) { pci_read_dword_ptr(&uma, PCI_ME_UMA); if (uma.valid) @@ -147,6 +148,13 @@ int intel_early_me_init_done(u8 status) pci_write_dword_ptr(&did, PCI_ME_H_GS); + /* + * The ME firmware does not respond with an ACK when NOMEM or ERROR + * are sent. + */ + if (status == ME_INIT_STATUS_NOMEM || status == ME_INIT_STATUS_ERROR) + return 0; + /* Must wait for ME acknowledgement */ for (count = ME_RETRY; count > 0; --count) { pci_read_dword_ptr(&hfs, PCI_ME_HFS); @@ -195,7 +203,9 @@ int intel_early_me_init_done(u8 status) /* Perform the requested reset */ if (reset) { outb(reset, 0xcf9); - hlt(); + while (1) { + hlt(); + } } return -1; } |