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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-09-21 08:28:23 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-09-22 18:31:03 +0000 |
| commit | 7eb0157fca33865783c1cc3c8e5cb2e327e551d7 (patch) | |
| tree | 537e678e9142692b9d391da13207b05ad19ba036 /src/southbridge/intel/lynxpoint/early_me.c | |
| parent | c88e370f851e686b5998fb3a0c44d7ace6dae7c3 (diff) | |
device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag
"Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)" note
4 says bit7 of byte 12 indicates whether the assembly supports self
refresh.
This patch decodes this and modifies decoding tRR accordingly.
Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_me.c')
0 files changed, 0 insertions, 0 deletions