diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 10:56:31 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-10 23:08:16 +0000 |
| commit | 8084b3856852f3fb3905e0fe4957b08518095d38 (patch) | |
| tree | c6aca7299eb82c0e6d5a2eba048a3373aa9fe9ca /src/southbridge/intel/lynxpoint/chip.h | |
| parent | b92df578b48911893a475b6f47ddfc574f63eac7 (diff) | |
sb/intel/lynxpoint/sata: Always use AHCI mode
The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/chip.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 40d0460419..89bbb1ce0c 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -38,9 +38,7 @@ struct southbridge_intel_lynxpoint_config { uint32_t gpe0_en_4; uint32_t alt_gp_smi_en; - /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; + /* SATA configuration */ uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; |