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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-29 05:12:56 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-20 09:24:35 +0000
commit780e02d1a54598f60f290e7eaba3c0456006ecce (patch)
tree334397f52b6f0d3edf300eb1fcf8c15415631ed5 /src/southbridge/intel/lynxpoint/acpi
parentc196246f75ae8fd235055250593fc7a78f5f3888 (diff)
ACPI GNVS: Drop APIC, factor out MPEN
APIC was not referenced anywhere in ASL. MPEN has references under boards: getac/p470, roda/rk9, roda/rk886ex. MPEN has reference also in Intel SpeedStep ASL. Replace static MPEN with detection of multiple CPUs installed. Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi')
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/globalnvs.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index 249954d857..758667d02d 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -54,8 +54,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TMPS, 8, // 0x25 - Temperature Sensor ID
/* Processor Identification */
Offset (0x28),
- APIC, 8, // 0x28 - APIC Enabled by coreboot
- MPEN, 8, // 0x29 - Multi Processor Enable
+ , 8, // 0x28 - Enabled by coreboot
+ , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state