diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-24 18:03:18 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-14 08:37:36 +0000 |
| commit | 2aaf7c0a1d1a895805772fe5f878606161c8d3c5 (patch) | |
| tree | 5d590e1379ec8098b6a8040a5357075d309f86c9 /src/southbridge/intel/lynxpoint/acpi/pch.asl | |
| parent | 2ead36334050ac692e64adc59a97320d8792adcc (diff) | |
haswell/lynxpoint: Align cosmetics with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/acpi/pch.asl')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index 6d0428c464..bace058387 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Intel Cougar Point PCH support */ +/* Intel Lynx Point PCH support */ -Scope(\) +Scope (\) { // Return TRUE if chipset is LynxPoint-LP Method (ISLP, 0, NotSerialized) @@ -11,17 +11,16 @@ Scope(\) } // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) + OperationRegion (IO_T, SystemIO, 0x800, 0x10) + Field (IO_T, ByteAcc, NoLock, Preserve) { - Offset(0x8), + Offset (0x8), TRP0, 8 // IO-Trap at 0x808 } - // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) - Field(RCRB, DWordAcc, Lock, Preserve) + // Root Complex Register Block + OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + Field (RCRB, DWordAcc, Lock, Preserve) { Offset(0x3404), // High Performance Timer Configuration HPAS, 2, // Address Select |