lynxpoint: Add ACPI Method to enable GPIO as wake source

This is an LPT-LP specific method that will enable a specific
GPIO as an ACPI SCI wake source.

It can be used by a device _DSW method to enable a pin that is
otherwise not configured to generate SCI at runtime.

It will set:
- GPIO owner to ACPI
- GPIO route to SCI
- GPIO config to GPIO, Input, Inverted

Also clean up and remove ACPI field definitions that are unused
and/or incorrect.

Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56621
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4189
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 94 insertions, 0 deletions

diff --git a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl
new file mode 100644
index 0000000000..fd64cb8cbc
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* LynxPoint-H */
+
+Scope (\_SB.PCI0.LPCB)
+{
+	// GWAK: Setup GPIO as ACPI GPE for Wake
+	// Arg0: GPIO Number
+	Method (GWAK, 1, NotSerialized)
+	{
+		// Local0 = GPIO Base Address
+		Store (And (GPBS, Not(0x1)), Local0)
+
+		// Local1 = BANK, Local2 = OFFSET
+		Divide (Arg0, 32, Local2, Local1)
+
+		//
+		// Set OWNER to ACPI
+		//
+
+		// Local3 = GPIOBASE + GPIO_OWN(BANK)
+		Store (Add (Local0, Multiply (Local1, 0x4)), Local3)
+
+		// GPIO_OWN(BANK)
+		OperationRegion (IOWN, SystemIO, Local3, 4)
+		Field (IOWN, AnyAcc, NoLock, Preserve) {
+			GOWN, 32,
+		}
+
+		// GPIO_OWN[GPIO] = 0 (ACPI)
+		Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN)
+
+		//
+		// Set ROUTE to SCI
+		//
+
+		// Local3 = GPIOBASE + GPIO_ROUTE(BANK)
+		Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3)
+
+		// GPIO_ROUTE(BANK)
+		OperationRegion (IROU, SystemIO, Local3, 4)
+		Field (IROU, AnyAcc, NoLock, Preserve) {
+			GROU, 32,
+		}
+
+		// GPIO_ROUTE[GPIO] = 0 (SCI)
+		Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU)
+
+		//
+		// Set GPnCONFIG to GPIO|INPUT|INVERT
+		//
+
+		// Local3 = GPIOBASE + GPnCONFIG0(GPIO)
+		Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3)
+
+		// GPnCONFIG(GPIO)
+		OperationRegion (GPNC, SystemIO, Local3, 8)
+		Field (GPNC, AnyAcc, NoLock, Preserve) {
+			GMOD, 1,  // MODE:   0=NATIVE 1=GPIO
+			, 1,
+			GIOS, 1,  // IO_SEL: 0=OUTPUT 1=INPUT
+			GINV, 1,  // INVERT: 0=NORMAL 1=INVERT
+			GLES, 1,  // LxEB:   0=EDGE 1=LEVEL
+			, 24,
+			ILVL, 1,  // INPUT:  0=LOW 1=HIGH
+			OLVL, 1,  // OUTPUT: 0=LOW 1=HIGH
+			GPWP, 2,  // PULLUP: 00=NONE 01=DOWN 10=UP 11=INVALID
+			ISEN, 1,  // SENSE:  0=ENABLE 1=DISABLE
+		}
+
+		Store (0x1, GMOD) // GPIO
+		Store (0x1, GIOS) // INPUT
+		Store (0x1, GINV) // INVERT
+	}
+}
\ No newline at end of file