diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-07-19 08:41:38 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 07:38:34 +0100 |
| commit | 80fd5c4461041508a9579d698ab89dd97ec2ae15 (patch) | |
| tree | ff3d6d56d297c587c2d7617714ae133973904f2f /src/southbridge/intel/lynxpoint/Kconfig | |
| parent | af98062817e61f4dafd509fd768696a4250f1aa3 (diff) | |
lynxpoint xhci: Add ACPI D0/D3 workarounds
There are specific programming requirements for the usb3 ports
on all LynxPoint chipsets when transitioning to D0 or D3.
LynxPoint-LP has additional workaround steps needed involving
resetting the disconnected ports when transitioning to D0.
The workarounds are implemented in ACPI code so the controller
can transition properly into D3 at runtime.
Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4374
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/Kconfig')
0 files changed, 0 insertions, 0 deletions