summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/ich5r/cmos_failover.c
diff options
context:
space:
mode:
authorStefan Reinauer <stepan@openbios.org>2006-04-06 21:37:10 +0000
committerStefan Reinauer <stepan@openbios.org>2006-04-06 21:37:10 +0000
commit966d0e6d70b20b6d14e265d59aaad37ce84d2ddb (patch)
tree70a4ea1fb8f3de6912dd6e2064f832bd5a393bbc /src/southbridge/intel/ich5r/cmos_failover.c
parent44f72eb3a3d07ec3c775b748f6a2a16e9e0a3e75 (diff)
break the tree really quick due to svn restrictions, next commit fill fix it
again. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/ich5r/cmos_failover.c')
-rw-r--r--src/southbridge/intel/ich5r/cmos_failover.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/southbridge/intel/ich5r/cmos_failover.c b/src/southbridge/intel/ich5r/cmos_failover.c
new file mode 100644
index 0000000000..9702313f9c
--- /dev/null
+++ b/src/southbridge/intel/ich5r/cmos_failover.c
@@ -0,0 +1,16 @@
+//kind of cmos_err for ich5
+#define RTC_FAILED (1 <<2)
+#define GEN_PMCON_3 0xa4
+static void check_cmos_failed(void)
+{
+
+ uint8_t byte;
+ byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
+ if( byte & RTC_FAILED){
+//clear bit 1 and bit 2
+ byte = cmos_read(RTC_BOOT_BYTE);
+ byte &= 0x0c;
+ byte |= MAX_REBOOT_CNT << 4;
+ cmos_write(byte, RTC_BOOT_BYTE);
+ }
+}