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authorStefan Reinauer <stepan@openbios.org>2006-04-06 21:37:10 +0000
committerStefan Reinauer <stepan@openbios.org>2006-04-06 21:37:10 +0000
commit966d0e6d70b20b6d14e265d59aaad37ce84d2ddb (patch)
tree70a4ea1fb8f3de6912dd6e2064f832bd5a393bbc /src/southbridge/intel/ich5r/chip.h
parent44f72eb3a3d07ec3c775b748f6a2a16e9e0a3e75 (diff)
break the tree really quick due to svn restrictions, next commit fill fix it
again. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/ich5r/chip.h')
-rw-r--r--src/southbridge/intel/ich5r/chip.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/southbridge/intel/ich5r/chip.h b/src/southbridge/intel/ich5r/chip.h
index b3abeabca7..eb63889794 100644
--- a/src/southbridge/intel/ich5r/chip.h
+++ b/src/southbridge/intel/ich5r/chip.h
@@ -1,4 +1,7 @@
-struct southbridge_intel_ich5r_config
+#ifndef I82801ER_CHIP_H
+#define I82801ER_CHIP_H
+
+struct southbridge_intel_i82801er_config
{
#define ICH5R_GPIO_USE_MASK 0x03
@@ -27,4 +30,7 @@ struct southbridge_intel_ich5r_config
unsigned int pirq_a_d;
unsigned int pirq_e_h;
};
-extern struct chip_operations southbridge_intel_ich5r_ops;
+extern struct chip_operations southbridge_intel_i82801er_ops;
+
+#endif /* I82801ER_CHIP_H */
+