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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-09-16 21:00:22 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-06 10:11:00 +0000 |
| commit | f503b60bb9f374741d6d262c4db04e4a4c3aaa0b (patch) | |
| tree | e300ef635ff92df77eb6e0cb2142f30541fc4288 /src/southbridge/intel/ibexpeak/Makefile.inc | |
| parent | e552d073b70dec6e6d27b2c575c92b1afb876a16 (diff) | |
sb/intel/ibexpeak: Add CIR initialization
This properly sets up the chipset initialization registers, instead of
replaying an RCBA dump.
The information is taken from the EDS and from the thinkpad x201
vendor BIOS disassembly and from an HP UEFI.
TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume
from S3.
Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/ibexpeak/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 83d083f3ae..97565d6bec 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,5 +42,6 @@ romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c endif |