From f503b60bb9f374741d6d262c4db04e4a4c3aaa0b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 16 Sep 2019 21:00:22 +0200 Subject: sb/intel/ibexpeak: Add CIR initialization This properly sets up the chipset initialization registers, instead of replaying an RCBA dump. The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI. TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3. Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/ibexpeak/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/southbridge/intel/ibexpeak/Makefile.inc') diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 83d083f3ae..97565d6bec 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -42,5 +42,6 @@ romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c +romstage-y += early_cir.c endif -- cgit v1.2.3