diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2013-06-10 09:53:33 -0700 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-26 19:08:48 +0100 |
commit | e807c34a5e34e8dd7cb959458de593ea1070fde4 (patch) | |
tree | 5b7ea1d5fb675add375221c745c585e9f6484a26 /src/southbridge/intel/i82870 | |
parent | 35bd3fedfeafe96b5fb938c1b47e2b0380fdbfb7 (diff) |
cmos post: Guard with spinlock
The CMOS post code storage mechanism does back-to-back
CMOS reads and writes that may be interleaved during
CPU bringup, leading to corruption of the log or of other
parts of CMOS.
Change-Id: I704813cc917a659fe034b71c2ff9eb9b80f7c949
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58102
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82870')
0 files changed, 0 insertions, 0 deletions