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authorDuncan Laurie <dlaurie@chromium.org>2012-12-17 11:29:10 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-14 18:24:32 +0100
commit045f153a4fe2b6e1cb193db01866218d0316f253 (patch)
tree653af6488dfe46d3b8d15d3df74740632b2b3cc5 /src/southbridge/intel/i82870/pcibridge.c
parent51254049b91a816c53b5cadf72d254f11e882818 (diff)
lynxpoint: Add new GPIO interface for Lynxpoint-LP
The low power variant of the chipset introduces a completely new interface to the GPIOs. This is a 1KB region and so needs to be moved as well so it does not conflict with other IO regions. Also expose the gpio_get functions to ramstage and move the prototypes to pch.h so they can be used for both GPIO interfaces. Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2648 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/i82870/pcibridge.c')
0 files changed, 0 insertions, 0 deletions