diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-31 19:22:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:22:46 +0200 |
| commit | ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch) | |
| tree | 9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/intel/i82870/pci_parity.c | |
| parent | 2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff) | |
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/i82870/pci_parity.c')
| -rw-r--r-- | src/southbridge/intel/i82870/pci_parity.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c index 71d2c538e9..b886c5244f 100644 --- a/src/southbridge/intel/i82870/pci_parity.c +++ b/src/southbridge/intel/i82870/pci_parity.c @@ -5,19 +5,19 @@ void p64h2_pci_parity_enable(void) { - uint8_t reg; + uint8_t reg; - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); + /* 2SERREN - SERR enable for PCI bridge secondary device */ + /* 2PEREN - Parity error for PCI bridge secondary device */ + pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®); + reg |= ((1 << 1) + (1 << 0)); + pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); - /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); + /* 2SERREN - SERR enable for PCI bridge secondary device */ + /* 2PEREN - Parity error for PCI bridge secondary device */ + pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®); + reg |= ((1 << 1) + (1 << 0)); + pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); - return; + return; } |