diff options
author | Yinghai Lu <yinghailu@gmail.com> | 2004-07-01 03:55:03 +0000 |
---|---|---|
committer | Yinghai Lu <yinghailu@gmail.com> | 2004-07-01 03:55:03 +0000 |
commit | 70093f7875371abe52c4417c6cc3a427d20781c5 (patch) | |
tree | f5812172eab817e66840583c669f16d4b1121531 /src/southbridge/intel/i82870/p64h2_pcibridge.c | |
parent | 7dea9552d5fa10c5542e744fe1d8e0a81689e3c1 (diff) |
Intel E7501 P64H2 ICH5R support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82870/p64h2_pcibridge.c')
-rw-r--r-- | src/southbridge/intel/i82870/p64h2_pcibridge.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82870/p64h2_pcibridge.c b/src/southbridge/intel/i82870/p64h2_pcibridge.c new file mode 100644 index 0000000000..6f161e900b --- /dev/null +++ b/src/southbridge/intel/i82870/p64h2_pcibridge.c @@ -0,0 +1,39 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <pc80/mc146818rtc.h> +#include "82870.h" + +static void p64h2_pcix_init(device_t dev) +{ + uint32_t dword; + uint16_t word; + uint8_t byte; + + + /* The purpose of changes to HCCR, ACNF, and MTT is to speed up the + PCI bus for cards having high speed transfers. */ + dword = 0xc2040002; + pci_write_config32(dev, HCCR, dword); + dword = 0x0000c3bf; + pci_write_config32(dev, ACNF, dword); + byte = 0x08; + pci_write_config8(dev, MTT, byte); + +} +static struct device_operations pcix_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = p64h2_pcix_init, + .scan_bus = pci_scan_bridge, +}; + +static struct pci_driver pcix_driver __pci_driver = { + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82870_1F0, +}; + |