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authorJoseph Smith <joe@settoplinux.org>2009-05-02 21:30:57 +0000
committerJoseph Smith <joe@smittys.pointclark.net>2009-05-02 21:30:57 +0000
commit4f0154c937fbf819e34ffbb3a71dc246fb6079c1 (patch)
tree13104ce4d780051378950d9fe30eb6b8cd27ecd6 /src/southbridge/intel/i82801xx/chip.h
parent88e71e88597d939972267cdb00aca3cc61f5e171 (diff)
Assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801xx/chip.h')
-rw-r--r--src/southbridge/intel/i82801xx/chip.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801xx/chip.h
index 309aa27ce6..d86c07e8e0 100644
--- a/src/southbridge/intel/i82801xx/chip.h
+++ b/src/southbridge/intel/i82801xx/chip.h
@@ -31,6 +31,18 @@
#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
struct southbridge_intel_i82801xx_config {
+ /**
+ * Interrupt Routing configuration
+ * If bit7 is 1, the interrupt is disabled.
+ */
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
};
extern struct chip_operations southbridge_intel_i82801xx_ops;