From 4f0154c937fbf819e34ffbb3a71dc246fb6079c1 Mon Sep 17 00:00:00 2001 From: Joseph Smith Date: Sat, 2 May 2009 21:30:57 +0000 Subject: Assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c. Signed-off-by: Joseph Smith Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i82801xx/chip.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/southbridge/intel/i82801xx/chip.h') diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801xx/chip.h index 309aa27ce6..d86c07e8e0 100644 --- a/src/southbridge/intel/i82801xx/chip.h +++ b/src/southbridge/intel/i82801xx/chip.h @@ -31,6 +31,18 @@ #define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H struct southbridge_intel_i82801xx_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; }; extern struct chip_operations southbridge_intel_i82801xx_ops; -- cgit v1.2.3