diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-12-29 06:26:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:21:34 +0000 |
| commit | 661ad4666ca0e78195f6901fce7b44a7e56e6331 (patch) | |
| tree | 57c25cee551ec747dcfdf0e38f995a091d5fcd79 /src/southbridge/intel/i82801jx | |
| parent | 286a0572e75ade325238617d15c136f74c4f67a4 (diff) | |
ACPI: Select ACPI_SOC_NVS only where suitable
Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.
Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.
Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Diffstat (limited to 'src/southbridge/intel/i82801jx')
| -rw-r--r-- | src/southbridge/intel/i82801jx/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/include/soc/nvs.h (renamed from src/southbridge/intel/i82801jx/nvs.h) | 0 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 7 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/smihandler.c | 3 |
5 files changed, 4 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 687cb45924..bd553eea76 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 9885bc0419..f4893c2ea4 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -23,4 +23,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801jx/include + endif diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index 96c0a40e05..96c0a40e05 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 26ba5d21e2..90650693e1 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -12,14 +12,12 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> #include <string.h> #include "chip.h" #include "i82801jx.h" -#include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> @@ -476,11 +474,6 @@ static void i82801jx_lpc_read_resources(struct device *dev) } } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 6a6c5b4c7f..03a6442eb1 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -4,11 +4,10 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> +#include <soc/nvs.h> #include <southbridge/intel/common/pmutil.h> #include "i82801jx.h" -#include "nvs.h" - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ |