From 661ad4666ca0e78195f6901fce7b44a7e56e6331 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 29 Dec 2020 06:26:21 +0200 Subject: ACPI: Select ACPI_SOC_NVS only where suitable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having some symmetry with now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Lance Zhao --- src/southbridge/intel/i82801jx/Kconfig | 1 + src/southbridge/intel/i82801jx/Makefile.inc | 2 + src/southbridge/intel/i82801jx/include/soc/nvs.h | 103 +++++++++++++++++++++++ src/southbridge/intel/i82801jx/lpc.c | 7 -- src/southbridge/intel/i82801jx/nvs.h | 103 ----------------------- src/southbridge/intel/i82801jx/smihandler.c | 3 +- 6 files changed, 107 insertions(+), 112 deletions(-) create mode 100644 src/southbridge/intel/i82801jx/include/soc/nvs.h delete mode 100644 src/southbridge/intel/i82801jx/nvs.h (limited to 'src/southbridge/intel/i82801jx') diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 687cb45924..bd553eea76 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ACPI_SOC_NVS select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 9885bc0419..f4893c2ea4 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -23,4 +23,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c +CPPFLAGS_common += -I$(src)/southbridge/intel/i82801jx/include + endif diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h new file mode 100644 index 0000000000..96c0a40e05 --- /dev/null +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_I82801JX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801JX_NVS_H +#include + +struct __packed global_nvs { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ + u8 lids; /* 0x0f - LID state (open = 1) */ + u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 dbgs; /* 0x11 - Debug state */ + u8 linx; /* 0x12 - Linux OS */ + u8 dckn; /* 0x13 - PCIe docking state */ + /* Thermal policy */ + u8 actt; /* 0x14 - active trip point */ + u8 tpsv; /* 0x15 - passive trip point */ + u8 tc1v; /* 0x16 - passive trip point TC1 */ + u8 tc2v; /* 0x17 - passive trip point TC2 */ + u8 tspv; /* 0x18 - passive trip point TSP */ + u8 tcrt; /* 0x19 - critical trip point */ + u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ + u8 dts1; /* 0x1b - DT sensor 1 */ + u8 flvl; /* 0x1c - current fan level */ + u8 rsvd2; + /* Battery Support */ + u8 bnum; /* 0x1e - number of batteries */ + u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */ + u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ + u8 rsvd3[3]; + /* Processor Identification */ + u8 apic; /* 0x28 - APIC enabled */ + u8 mpen; /* 0x29 - MP capable/enabled */ + u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ + u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ + u8 ppcm; /* 0x2c - Max. PPC state */ + u8 rsvd4[5]; + /* Super I/O & CMOS config */ + u8 natp; /* 0x32 - SIO type */ + u8 cmap; /* 0x33 - */ + u8 cmbp; /* 0x34 - */ + u8 lptp; /* 0x35 - LPT port */ + u8 fdcp; /* 0x36 - Floppy Disk Controller */ + u8 rfdv; /* 0x37 - */ + u8 hotk; /* 0x38 - Hot Key */ + u8 rtcf; + u8 util; + u8 acin; + /* Integrated Graphics Device */ + u8 igds; /* 0x3c - IGD state */ + u8 tlst; /* 0x3d - Display Toggle List Pointer */ + u8 cadl; /* 0x3e - currently attached devices */ + u8 padl; /* 0x3f - previously attached devices */ + u8 rsvd5[36]; + /* Backlight Control */ + u8 blcs; /* 0x64 - Backlight Control possible */ + u8 brtl; + u8 odds; + u8 rsvd6[0x7]; + /* Ambient Light Sensors*/ + u8 alse; /* 0x6e - ALS enable */ + u8 alaf; + u8 llow; + u8 lhih; + u8 rsvd7[0x6]; + /* EMA */ + u8 emae; /* 0x78 - EMA enable */ + u16 emap; + u16 emal; + u8 rsvd8[0x5]; + /* MEF */ + u8 mefe; /* 0x82 - MEF enable */ + u8 rsvd9[0x9]; + /* TPM support */ + u8 tpmp; /* 0x8c - TPM */ + u8 tpme; + u8 rsvd10[8]; + /* SATA */ + u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ + u8 gtf1[7]; + u8 gtf2[7]; + u8 idem; + u8 idet; + u8 rsvd11[67]; + /* Mainboard specific */ + u8 dock; /* 0xf0 - Docking Status */ + u8 bten; + + u32 cbmc; + u8 rsvd13[10]; +}; + +#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 26ba5d21e2..90650693e1 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -12,14 +12,12 @@ #include #include #include -#include #include #include #include #include #include "chip.h" #include "i82801jx.h" -#include "nvs.h" #include #include #include @@ -476,11 +474,6 @@ static void i82801jx_lpc_read_resources(struct device *dev) } } -size_t gnvs_size_of_array(void) -{ - return sizeof(struct global_nvs); -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h deleted file mode 100644 index 96c0a40e05..0000000000 --- a/src/southbridge/intel/i82801jx/nvs.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOUTHBRIDGE_INTEL_I82801JX_NVS_H -#define SOUTHBRIDGE_INTEL_I82801JX_NVS_H -#include - -struct __packed global_nvs { - /* Miscellaneous */ - u16 osys; /* 0x00 - Operating System */ - u8 smif; /* 0x02 - SMI function call ("TRAP") */ - u8 prm0; /* 0x03 - SMI function call parameter */ - u8 prm1; /* 0x04 - SMI function call parameter */ - u8 scif; /* 0x05 - SCI function call (via _L00) */ - u8 prm2; /* 0x06 - SCI function call parameter */ - u8 prm3; /* 0x07 - SCI function call parameter */ - u8 lckf; /* 0x08 - Global Lock function for EC */ - u8 prm4; /* 0x09 - Lock function parameter */ - u8 prm5; /* 0x0a - Lock function parameter */ - u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ - u8 lids; /* 0x0f - LID state (open = 1) */ - u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 dbgs; /* 0x11 - Debug state */ - u8 linx; /* 0x12 - Linux OS */ - u8 dckn; /* 0x13 - PCIe docking state */ - /* Thermal policy */ - u8 actt; /* 0x14 - active trip point */ - u8 tpsv; /* 0x15 - passive trip point */ - u8 tc1v; /* 0x16 - passive trip point TC1 */ - u8 tc2v; /* 0x17 - passive trip point TC2 */ - u8 tspv; /* 0x18 - passive trip point TSP */ - u8 tcrt; /* 0x19 - critical trip point */ - u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ - u8 dts1; /* 0x1b - DT sensor 1 */ - u8 flvl; /* 0x1c - current fan level */ - u8 rsvd2; - /* Battery Support */ - u8 bnum; /* 0x1e - number of batteries */ - u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */ - u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ - u8 rsvd3[3]; - /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ - u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ - u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ - u8 ppcm; /* 0x2c - Max. PPC state */ - u8 rsvd4[5]; - /* Super I/O & CMOS config */ - u8 natp; /* 0x32 - SIO type */ - u8 cmap; /* 0x33 - */ - u8 cmbp; /* 0x34 - */ - u8 lptp; /* 0x35 - LPT port */ - u8 fdcp; /* 0x36 - Floppy Disk Controller */ - u8 rfdv; /* 0x37 - */ - u8 hotk; /* 0x38 - Hot Key */ - u8 rtcf; - u8 util; - u8 acin; - /* Integrated Graphics Device */ - u8 igds; /* 0x3c - IGD state */ - u8 tlst; /* 0x3d - Display Toggle List Pointer */ - u8 cadl; /* 0x3e - currently attached devices */ - u8 padl; /* 0x3f - previously attached devices */ - u8 rsvd5[36]; - /* Backlight Control */ - u8 blcs; /* 0x64 - Backlight Control possible */ - u8 brtl; - u8 odds; - u8 rsvd6[0x7]; - /* Ambient Light Sensors*/ - u8 alse; /* 0x6e - ALS enable */ - u8 alaf; - u8 llow; - u8 lhih; - u8 rsvd7[0x6]; - /* EMA */ - u8 emae; /* 0x78 - EMA enable */ - u16 emap; - u16 emal; - u8 rsvd8[0x5]; - /* MEF */ - u8 mefe; /* 0x82 - MEF enable */ - u8 rsvd9[0x9]; - /* TPM support */ - u8 tpmp; /* 0x8c - TPM */ - u8 tpme; - u8 rsvd10[8]; - /* SATA */ - u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ - u8 gtf1[7]; - u8 gtf2[7]; - u8 idem; - u8 idet; - u8 rsvd11[67]; - /* Mainboard specific */ - u8 dock; /* 0xf0 - Docking Status */ - u8 bten; - - u32 cbmc; - u8 rsvd13[10]; -}; - -#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 6a6c5b4c7f..03a6442eb1 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -4,11 +4,10 @@ #include #include #include +#include #include #include "i82801jx.h" -#include "nvs.h" - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ -- cgit v1.2.3