summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801jx/pcie.c
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-03-25 09:53:23 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-13 09:29:33 +0000
commit9005071c5fb1d75b2a54aa0b3e7af47e25d2de54 (patch)
tree507bada945aaf0c67dbe0dcbb823c97b569be4f4 /src/southbridge/intel/i82801jx/pcie.c
parent5709e03613b342f9dc00a659b6474c6ee510fcc3 (diff)
nb/intel/sandybridge: Move boot_count_increment()
Move boot_count_increment() to romstage.c, drop preprocessor code and only increase counter once on regular boot. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32067 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/pcie.c')
0 files changed, 0 insertions, 0 deletions