diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-01-30 11:56:52 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-02-04 21:17:57 +0000 |
| commit | f56249ba0b1cf4bf83d93f3d717d3eb8a0624ff2 (patch) | |
| tree | 6a80ae02764c4d85422846c83a52c07709bdf79b /src/southbridge/intel/i82801jx/acpi/lpc.asl | |
| parent | aaac678e800dd9a6c0b2ca63d3cebfb3005628f8 (diff) | |
soc/amd/stoneyridge: Reboot if missing MRC cache info
AGESA doesn't detect invalid NV data during AmdInitResume(). In
cases where the data has been erased, or cannot be found, reboot
the system. Otherwise the user will experience a hang when cbmem
isn't recovered and the postcar frame cannot be initialized.
BUG=b:122725586
TEST=Write S3 NV save data with 0xff and force reboot
Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/acpi/lpc.asl')
0 files changed, 0 insertions, 0 deletions