diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-09 20:48:37 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-21 15:44:19 +0000 |
| commit | 349e08535a7666cabe52ebc331e3bce5468b786b (patch) | |
| tree | 6e337227e7450ac1d931ac61eaf939ae936ad50c /src/southbridge/intel/i82801jx/acpi/lpc.asl | |
| parent | 7b9c139ac26eded525980e896b354c99c08cdca7 (diff) | |
sb/intel/i82801jx: Add correct PCI ids and change names
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/acpi/lpc.asl')
| -rw-r--r-- | src/southbridge/intel/i82801jx/acpi/lpc.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index 9d27b0b482..1d9e54e237 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -170,8 +170,8 @@ Device (LPCB) IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH9 ACPI - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH9 GPIO + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH10 ACPI + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH10 GPIO }) } |