diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-06 08:04:28 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-22 14:13:42 +0000 |
| commit | 04a40379b0cbc96c25498ec69520cb7cd85f3fe4 (patch) | |
| tree | 49ca87768e1eba294f244ea84158a32992056065 /src/southbridge/intel/i82801ix | |
| parent | e8601f47772c9a71486e15e19c2cdd2947034b49 (diff) | |
sb,soc/intel: Set IOAPIC redirection entry count
The number of redirection table entries (aka interrupt vectors) inside
an I/O APIC may depend of the SKU, with the related register being of
type read/write-once. Provide support utilities to either lock or set
this registers value.
Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
| -rw-r--r-- | src/southbridge/intel/i82801ix/lpc.c | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 866ede9a50..21f1faa3b7 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -27,20 +27,13 @@ typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_apic(struct device *dev) { - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Enable IOAPIC. Keep APIC Range Select at zero. */ RCBA8(0x31ff) = 0x03; /* We have to read 0x31ff back if bit0 changed. */ RCBA8(0x31ff); /* Lock maximum redirection entries (MRE), R/WO register. */ - *ioapic_index = 0x01; - reg32 = *ioapic_data; - *ioapic_index = 0x01; - *ioapic_data = reg32; + ioapic_lock_max_vectors(VIO_APIC_VADDR); setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */ } |