diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 11:13:42 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 01:10:17 +0000 |
| commit | 6740647cfd2d8ff8840d1e2ab37b66ce14b19180 (patch) | |
| tree | d2486eca3a88ef1141aaeba3d0774df247483d83 /src/southbridge/intel/i82801ix/bootblock.c | |
| parent | e36733bf849e781d6e86a7549f2c17d246e619ac (diff) | |
sb/intel/i82801ix: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Ie05f484cf4b346601e6128c95ff2b27ce59b995f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42188
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801ix/bootblock.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/bootblock.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 262b513d5e..b7461bb97c 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -4,18 +4,9 @@ #include <device/pci_ops.h> #include "i82801ix.h" - static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); } void bootblock_early_southbridge_init(void) |