diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-09-10 21:06:40 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 14:41:51 +0000 |
| commit | 08b5ef48346a0040d5d90b1fe1a9fd3e96b6a358 (patch) | |
| tree | 19f16e89bb72987e18ab3ee05a066aed1ed1463c /src/southbridge/intel/i82801gx | |
| parent | 30a94751925dda7b662643c87a35a95b011d2349 (diff) | |
sb/intel/i82801gx/acpi: Convert *.asl to ASL 2.0 syntax
Also remove extra empty lines.
It builds same binary for apple/macbook21 using BUILD_TIMELESS=1
Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45275
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/lpc.asl | 14 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/usb.asl | 20 |
2 files changed, 15 insertions, 19 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index b93fa96d23..1f9e701e84 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -73,7 +73,7 @@ Device (LPCB) If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ Device (LPCB) { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801gx/acpi/usb.asl b/src/southbridge/intel/i82801gx/acpi/usb.asl index 16db17595d..7c4ef345de 100644 --- a/src/southbridge/intel/i82801gx/acpi/usb.asl +++ b/src/southbridge/intel/i82801gx/acpi/usb.asl @@ -21,9 +21,9 @@ Device (USB1) { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -40,7 +40,6 @@ Device (USB1) } } - // USB Controller 0:1d.1 Device (USB2) @@ -60,9 +59,9 @@ Device (USB2) { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -80,7 +79,6 @@ Device (USB2) } - // USB Controller 0:1d.2 Device (USB3) @@ -100,9 +98,9 @@ Device (USB3) { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -120,7 +118,6 @@ Device (USB3) } - // USB Controller 0:1d.3 Device (USB4) @@ -140,9 +137,9 @@ Device (USB4) { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U4WE) + U4WE = 3 } Else { - Store (0, U4WE) + U4WE = 0 } } @@ -160,7 +157,6 @@ Device (USB4) } - // EHCI Controller 0:1d.7 Device (EHC1) |