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authorArthur Heymans <arthur@aheymans.xyz>2018-03-28 18:49:27 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-04 09:35:54 +0000
commit02c997122f5f070c2196b86799fa77c85cc22383 (patch)
tree0e4e1c225a1f63f08d9b19d9a4ccf16de2bfa681 /src/southbridge/intel/i82801gx
parent93ffe83ec292754988df346e8e51e8f2c8ac7283 (diff)
src/sb/intel/common/spi.c: Adapt and link in romstage
Based on Nicola Corna's work. This allows for CONFIG_CONSOLE_SPI_FLASH to be used, which writes the console output to the SPI flash. TESTED to still work in ramstage on x220 (correctly writes MRC CACHE), the option CONFIG_CONSOLE_SPI_FLASH compiles for targets using the common Intel SPI code (untested though). Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
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