diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-02-22 06:09:43 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-02-22 06:09:43 +0000 |
| commit | de3206a7bebce99f11e753164cc4d46357bba96a (patch) | |
| tree | 9843d883940e372dd357b1357ecd7eaba3e3365f /src/southbridge/intel/i82801gx/i82801gx_pci.c | |
| parent | d650e9934ff8da9b9cb69e42e642c0ee6d390bf6 (diff) | |
This is a general cleanup patch
- drop include/part and move files to include/
- get rid lots of warnings
- make resource allocator happy with w83627thg
- trivial cbmem resume fix
- fix payload and log level settings in abuild
- fix kontron mptable for virtual wire mode
- drop some dead includes and dead code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx_pci.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_pci.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c index 215563d9c2..d9057cb295 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_pci.c +++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "i82801gx.h" static void pci_init(struct device *dev) { @@ -34,31 +35,31 @@ static void pci_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, reg16); /* This device has no interrupt */ - pci_write_config8(dev, 0x3c, 0xff); + pci_write_config8(dev, INTR, 0xff); /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, 0x3e); + reg16 = pci_read_config16(dev, BCTRL); reg16 &= ~(1 << 0); reg16 &= ~(1 << 1); - pci_write_config16(dev, 0x3e, reg16); + pci_write_config16(dev, BCTRL, reg16); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, 0x1b); + reg8 = pci_read_config8(dev, SMLT); reg8 &= 0x07; reg8 |= (0x04 << 3); - pci_write_config8(dev, 0x1b, reg8); + pci_write_config8(dev, SMLT, reg8); /* Will this improve throughput of bus masters? */ pci_write_config8(dev, PCI_MIN_GNT, 0x06); /* Clear errors in status registers */ - reg16 = pci_read_config16(dev, 0x06); + reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; - pci_write_config16(dev, 0x06, reg16); + pci_write_config16(dev, PSTS, reg16); - reg16 = pci_read_config16(dev, 0x1e); + reg16 = pci_read_config16(dev, SECSTS); // reg16 |= 0xf900; - pci_write_config16(dev, 0x1e, reg16); + pci_write_config16(dev, SECSTS, reg16); } #undef PCI_BRIDGE_UPDATE_COMMAND |