diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 12:32:54 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 21:33:35 +0000 |
| commit | d19332ca3a68eeadcae73d5660834bcaadf02030 (patch) | |
| tree | a9d216831bbb150523db9bf803b4aa9afc7ad67f /src/southbridge/intel/i82801gx/early_init.c | |
| parent | 302a1437cd4393961cc8cca02fb56e64a9a73043 (diff) | |
sb/intel/i82801gx: Use PCI bitwise ops
While we are at it, also reflow a few lines that fit in 96 characters.
Tested with BUILD_TIMELESS=1, Getac P470 does not change.
Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/i82801gx/early_init.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_init.c | 19 |
1 files changed, 4 insertions, 15 deletions
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index ef48ed857a..72281ea5f3 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -61,9 +61,6 @@ void i82801gx_setup_bars(void) #if ENV_ROMSTAGE void i82801gx_early_init(void) { - uint8_t reg8; - uint32_t reg32; - enable_smbus(); printk(BIOS_DEBUG, "Setting up static southbridge registers..."); @@ -83,22 +80,14 @@ void i82801gx_early_init(void) pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, ~RTC_BATTERY_DEAD); /* USB transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_or_config8(PCI_DEV(0, 0x1f, 0), 0xad, 3 << 0); - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xfc, (1 << 29) | (1 << 17)); - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + pci_or_config32(PCI_DEV(0, 0x1d, 7), 0xdc, (1 << 31) | (1 << 27)); /* Enable IOAPIC */ RCBA8(OIC) = 0x03; |