diff options
| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2014-04-14 12:47:37 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-16 23:25:37 +0100 |
| commit | d712ec47d48f765dbc9008d94b58842d6c24b544 (patch) | |
| tree | 2ee734f118188fd0446f88e1a67264ce07fb9ef9 /src/southbridge/intel/i82801gx/chip.h | |
| parent | 84b8be6a97806bb4a98846ef449440f6950de727 (diff) | |
nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 register
This register needs to be set properly during display init.
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
nyan_big display works as well. However, the mode setting
needs to be based on either devicetree or EDID.
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031
Original-Reviewed-on: https://chromium-review.googlesource.com/194739
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c
Reviewed-on: http://review.coreboot.org/7767
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/i82801gx/chip.h')
0 files changed, 0 insertions, 0 deletions