drop extra whitespace at end of line for i945 + ICH7 (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

11 files changed, 32 insertions, 32 deletions

diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index 368e90679f..5ac1c83cd6 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -24,7 +24,7 @@
 Name(\PICM, 0)		// IOAPIC/8259
 Name(\DSEN, 1)		// Display Output Switching Enable
 
-/* Global ACPI memory region. This region is used for passing information 
+/* Global ACPI memory region. This region is used for passing information
  * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
  * Since we don't know where this will end up in memory at ACPI compile time,
  * we have to fix it up in coreboot's ACPI creation phase.
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index dd3bc87e2f..3f845c483b 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -108,7 +108,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select 
+		HPAS, 2, 	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
@@ -135,7 +135,7 @@ Scope(\)
 		RP5D, 1,	// Root Port 5 disable
 		RP6D, 1		// Root Port 6 disable
 	}
-	
+
 }
 
 // 0:1b.0 High Definition Audio (Azalia)
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl b/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
index 7f76ccc786..8a8cf82217 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_ac97.asl
@@ -33,7 +33,7 @@ Device (AUD0)
 Device (MODM)
 {
 	Name (_ADR, 0x001e0003)
-	
+
 	Name (_PRW, Package(){ 5, 4 })
 }
 
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl b/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
index 5b8b386c39..d03be4fdd3 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_audio.asl
@@ -28,7 +28,7 @@ Device (HDEF)
 	Name (_ADR, 0x001b0000)
 
 	// Power Resources for Wake
-	Name (_PRW, Package(){ 
+	Name (_PRW, Package(){
 		5,  // Bit 5 of GPE
 		4   // Can wake from S4 state.
 	})
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl b/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl
index e993dd30cd..5fcee45f29 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl
@@ -36,7 +36,7 @@ Device (LNKA)
 		IRQ(Level, ActiveLow, Shared)
 			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
 	})
-	
+
 	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
@@ -95,7 +95,7 @@ Device (LNKB)
 		IRQ(Level, ActiveLow, Shared)
 			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
 	})
-	
+
 	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
@@ -154,7 +154,7 @@ Device (LNKC)
 		IRQ(Level, ActiveLow, Shared)
 			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
 	})
-	
+
 	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
@@ -213,7 +213,7 @@ Device (LNKD)
 		IRQ(Level, ActiveLow, Shared)
 			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
 	})
-	
+
 	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
@@ -272,7 +272,7 @@ Device (LNKE)
 		IRQ(Level, ActiveLow, Shared)
 			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
 	})
-	
+
 	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
@@ -331,7 +331,7 @@ Device (LNKF)
 		IRQ(Level, ActiveLow, Shared)
 			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
 	})
-	
+
 	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
@@ -390,7 +390,7 @@ Device (LNKG)
 		IRQ(Level, ActiveLow, Shared)
 			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
 	})
-	
+
 	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
@@ -449,7 +449,7 @@ Device (LNKH)
 		IRQ(Level, ActiveLow, Shared)
 			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
 	})
-	
+
 	// Current Resource Settings for this link
 	Method (_CRS, 0, Serialized)
 	{
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl b/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
index d5705396ce..fdf05b2e2f 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
@@ -24,7 +24,7 @@
 Device (LPCB)
 {
 	Name(_ADR, 0x001f0000)
-	
+
 	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
 	Field (LPC0, AnyAcc, NoLock, Preserve)
 	{
@@ -52,7 +52,7 @@ Device (LPCB)
 	}
 
 	Include ("../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl")
-	
+
 	Include ("acpi/ec.asl")
 
 	Device (DMAC)		// DMA Controller
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl b/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl
index f12522a807..1905ed26d2 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_pata.asl
@@ -41,7 +41,7 @@ Device (PATA)
 			CreateDwordField (PBUF,  4, DMA0)
 			CreateDwordField (PBUF,  8, PIO1)
 			CreateDwordField (PBUF, 12, DMA1)
-			CreateDwordField (PBUF, 16, FLAG) 
+			CreateDwordField (PBUF, 16, FLAG)
 
 			// TODO fill return structure
 
@@ -55,7 +55,7 @@ Device (PATA)
 			CreateDwordField (Arg0,  4, DMA0)
 			CreateDwordField (Arg0,  8, PIO1)
 			CreateDwordField (Arg0, 12, DMA1)
-			CreateDwordField (Arg0, 16, FLAG) 
+			CreateDwordField (Arg0, 16, FLAG)
 
 			// TODO: Do the deed
 		}
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
index 775a34dfe8..9bcf58e413 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
@@ -64,7 +64,7 @@ Device (PCIB)
 	// TODO: How many slots, where?
 
 	// PCI Interrupt Routing.
-	// If PICM is set, interrupts are routed over the i8259, otherwise 
+	// If PICM is set, interrupts are routed over the i8259, otherwise
 	// over the IOAPIC. (Really? If they're above 15 they need to be routed
 	// fixed over the IOAPIC?)
 
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl b/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl
index bf7a06a895..e0c336ac5d 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_sata.asl
@@ -44,7 +44,7 @@ Device (SATA)
 			CreateDwordField (PBUF,  4, DMA0)
 			CreateDwordField (PBUF,  8, PIO1)
 			CreateDwordField (PBUF, 12, DMA1)
-			CreateDwordField (PBUF, 16, FLAG) 
+			CreateDwordField (PBUF, 16, FLAG)
 
 			// TODO fill return structure
 
@@ -58,7 +58,7 @@ Device (SATA)
 			CreateDwordField (Arg0,  4, DMA0)
 			CreateDwordField (Arg0,  8, PIO1)
 			CreateDwordField (Arg0, 12, DMA1)
-			CreateDwordField (Arg0, 16, FLAG) 
+			CreateDwordField (Arg0, 16, FLAG)
 
 			// TODO: Do the deed
 		}
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl b/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
index 6b1009c24a..b7d807ee44 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
@@ -24,7 +24,7 @@
 Device (SBUS)
 {
 	Name (_ADR, 0x001f0003)
-	
+
 	OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
 	Field(SMBP, DWordAcc, NoLock, Preserve)
 	{
@@ -102,7 +102,7 @@ Device (SBUS)
 				Store (0, Local0)	// We're ready
 			}
 		}
-		
+
 		Store (4000, Local0)	// Timeout 200ms (50us * 4000)
 		While (Local0) {
 			If (And (HSTS, 0x01)) {		// Host Busy?
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl b/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl
index 99a2cb9571..9ae9909a9e 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_usb.asl
@@ -26,7 +26,7 @@
 Device (USB1)
 {
 	Name(_ADR, 0x001d0000)
-	
+
 	OperationRegion(U01P, PCI_Config, 0, 256)
 	Field(U01P, DWordAcc, NoLock, Preserve)
 	{
@@ -35,7 +35,7 @@ Device (USB1)
 	}
 
 	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
-	
+
 	Method (_PSW, 1)	// Power State Wake method
 	{
 		// USB Controller can wake OS from Sleep State
@@ -65,7 +65,7 @@ Device (USB1)
 Device (USB2)
 {
 	Name(_ADR, 0x001d0001)
-	
+
 	OperationRegion(U02P, PCI_Config, 0, 256)
 	Field(U02P, DWordAcc, NoLock, Preserve)
 	{
@@ -74,7 +74,7 @@ Device (USB2)
 	}
 
 	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
-	
+
 	Method (_PSW, 1)	// Power State Wake method
 	{
 		// USB Controller can wake OS from Sleep State
@@ -105,7 +105,7 @@ Device (USB2)
 Device (USB3)
 {
 	Name(_ADR, 0x001d0002)
-	
+
 	OperationRegion(U03P, PCI_Config, 0, 256)
 	Field(U03P, DWordAcc, NoLock, Preserve)
 	{
@@ -114,7 +114,7 @@ Device (USB3)
 	}
 
 	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
-	
+
 	Method (_PSW, 1)	// Power State Wake method
 	{
 		// USB Controller can wake OS from Sleep State
@@ -145,7 +145,7 @@ Device (USB3)
 Device (USB4)
 {
 	Name(_ADR, 0x001d0003)
-	
+
 	OperationRegion(U04P, PCI_Config, 0, 256)
 	Field(U04P, DWordAcc, NoLock, Preserve)
 	{
@@ -154,7 +154,7 @@ Device (USB4)
 	}
 
 	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
-	
+
 	Method (_PSW, 1)	// Power State Wake method
 	{
 		// USB Controller can wake OS from Sleep State
@@ -185,9 +185,9 @@ Device (USB4)
 Device (EHC1)
 {
 	Name(_ADR, 0x001d0007)
-	
+
 	Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
-	
+
 	// Leave USB ports on for to allow Wake from USB
 
 	Method(_S3D,0)	// Highest D State in S3 State