aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801ex/reset.c
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2016-08-31 19:22:16 +0200
committerMartin Roth <martinroth@google.com>2016-08-31 20:22:46 +0200
commitba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch)
tree9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/intel/i82801ex/reset.c
parent2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff)
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/i82801ex/reset.c')
-rw-r--r--src/southbridge/intel/i82801ex/reset.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c
index 9936892efe..8036ffde17 100644
--- a/src/southbridge/intel/i82801ex/reset.c
+++ b/src/southbridge/intel/i82801ex/reset.c
@@ -3,6 +3,6 @@
void hard_reset(void)
{
- /* Try rebooting through port 0xcf9 */
- outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+ /* Try rebooting through port 0xcf9 */
+ outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
}