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authorarch import user (historical) <svn@openbios.org>2005-07-06 17:17:25 +0000
committerarch import user (historical) <svn@openbios.org>2005-07-06 17:17:25 +0000
commit6ca7636c8f52560e732cdd5b1c7829cda5aa2bde (patch)
treecc45ae7c4dea6e2c5338f52b4314106bf07023be /src/southbridge/intel/i82801er
parentb2ed53dd5669c2c3839633bd2b3b4af709a5b149 (diff)
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801er')
-rw-r--r--src/southbridge/intel/i82801er/i82801er_early_smbus.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801er/i82801er_early_smbus.c b/src/southbridge/intel/i82801er/i82801er_early_smbus.c
index ed014f1a86..d923f674ac 100644
--- a/src/southbridge/intel/i82801er/i82801er_early_smbus.c
+++ b/src/southbridge/intel/i82801er/i82801er_early_smbus.c
@@ -46,6 +46,21 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
+static int smbus_wait_until_active(void)
+{
+ unsigned long loops;
+ loops = SMBUS_TIMEOUT;
+ do {
+ unsigned char val;
+ smbus_delay();
+ val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
+ if ((val & 1)) {
+ break;
+ }
+ } while(--loops);
+ return loops?0:-4;
+}
+
static int smbus_wait_until_ready(void)
{
unsigned long loops;
@@ -113,6 +128,10 @@ static int smbus_read_byte(unsigned device, unsigned address)
/* start a byte read, with interrupts disabled */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
+ /* poll for it to start */
+ if (smbus_wait_until_active() < 0) {
+ return -4;
+ }
/* poll for transaction completion */
if (smbus_wait_until_done() < 0) {