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| author | Yinghai Lu <yinghailu@gmail.com> | 2004-07-01 03:55:03 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2004-07-01 03:55:03 +0000 |
| commit | 70093f7875371abe52c4417c6cc3a427d20781c5 (patch) | |
| tree | f5812172eab817e66840583c669f16d4b1121531 /src/southbridge/intel/i82801er/i82801er_sata.c | |
| parent | 7dea9552d5fa10c5542e744fe1d8e0a81689e3c1 (diff) | |
Intel E7501 P64H2 ICH5R support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801er/i82801er_sata.c')
| -rw-r--r-- | src/southbridge/intel/i82801er/i82801er_sata.c | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801er/i82801er_sata.c b/src/southbridge/intel/i82801er/i82801er_sata.c new file mode 100644 index 0000000000..b00231e459 --- /dev/null +++ b/src/southbridge/intel/i82801er/i82801er_sata.c @@ -0,0 +1,75 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "i82801er.h" + +static void sata_init(struct device *dev) +{ + + uint16_t word; + uint8_t byte; + int enable_c=1, enable_d=1; + int i; + + //Enable Serial ATA port + byte = pci_read_config8(dev,0x90); + byte &= 0xf8; + byte |= ICH5_SATA_ADDRESS_MAP & 7; + pci_write_config8(dev,0x90,byte); + +// for(i=0;i<10;i++) { + word = pci_read_config16(dev,0x92); + word &= 0xfffc; +// if( (word & 0x0003) == 0x0003) break; + word |= 0x0003; // enable P0/P1 + pci_write_config16(dev,0x92,word); +// } + +// for(i=0;i<10;i++) { + /* enable ide0 */ + word = pci_read_config16(dev, 0x40); + word &= ~(1 << 15); + if(enable_c==0) { +// if( (word & 0x8000) == 0x0000) break; + word |= 0x0000; + } + else { +// if( (word & 0x8000) == 0x8000) break; + word |= 0x8000; + } + pci_write_config16(dev, 0x40, word); +// } + /* enable ide1 */ +// for(i=0;i<10;i++) { + word = pci_read_config16(dev, 0x42); + word &= ~(1 << 15); + if(enable_d==0) { +// if( (word & 0x8000) == 0x0000) break; + word |= 0x0000; + } + else { +// if( (word & 0x8000) == 0x8000) break; + word |= 0x8000; + } + pci_write_config16(dev, 0x42, word); +// } + +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .scan_bus = 0, + .enable = i82801er_enable, +}; + +static struct pci_driver stat_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801ER_1F2_R, +}; + |