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authorStefan Reinauer <stepan@openbios.org>2006-04-06 21:40:36 +0000
committerStefan Reinauer <stepan@openbios.org>2006-04-06 21:40:36 +0000
commit84e4bf69c7f0b6b4cf685fe0d6abf6ec93b2eff5 (patch)
tree716c33a7500dba12b30b3306656afd75824a5266 /src/southbridge/intel/i82801er/cmos_failover.c
parent966d0e6d70b20b6d14e265d59aaad37ce84d2ddb (diff)
interesting behavior, i thought svn could do moves.
the result should be ok though.. the purpose is dropping the old i82801er southbridge code and using the ich5r code instead because its the same chip but the code looks more solid and is used by many more systems. Some of the old i82801er features have been ported (like hpet enable) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801er/cmos_failover.c')
-rw-r--r--src/southbridge/intel/i82801er/cmos_failover.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801er/cmos_failover.c b/src/southbridge/intel/i82801er/cmos_failover.c
new file mode 100644
index 0000000000..9702313f9c
--- /dev/null
+++ b/src/southbridge/intel/i82801er/cmos_failover.c
@@ -0,0 +1,16 @@
+//kind of cmos_err for ich5
+#define RTC_FAILED (1 <<2)
+#define GEN_PMCON_3 0xa4
+static void check_cmos_failed(void)
+{
+
+ uint8_t byte;
+ byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
+ if( byte & RTC_FAILED){
+//clear bit 1 and bit 2
+ byte = cmos_read(RTC_BOOT_BYTE);
+ byte &= 0x0c;
+ byte |= MAX_REBOOT_CNT << 4;
+ cmos_write(byte, RTC_BOOT_BYTE);
+ }
+}