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author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-16 14:17:02 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-18 16:36:33 +0000 |
commit | 58a5374d5fbf2ddccbd5a2b156ac1a4b44b91522 (patch) | |
tree | 99683e76ff1ecbb30a5aa63e2707c40b5c38e5ca /src/southbridge/intel/i82801dx/fadt.c | |
parent | 61f22cff5916dc528690721aa3aaa88f9c6576ad (diff) |
sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree
Since the PCIe root ports in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.
TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are
visible and working.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/southbridge/intel/i82801dx/fadt.c')
0 files changed, 0 insertions, 0 deletions