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authorDivagar Mohandass <divagar.mohandass@intel.com>2015-09-08 15:03:45 +0530
committerMartin Roth <martinroth@google.com>2016-01-28 00:02:15 +0100
commit39f84fa6623f8981816682138d02acf3c31f3672 (patch)
tree4f95ac5c8d782b75cd9b902317d70c3f7fb7b593 /src/southbridge/intel/i82801dx/early_smbus.c
parent4f4c6e88be48d62c41c88bc5b36828c967e0d6e4 (diff)
intel/strago: Clean up DDR configuration.
This change includes following changes: - Clean up the DDR configuration and flow. - Removing support for non LPDDR3 boards. - Supporting only LPDDR3 and PMIC config. TEST=Build/flash CB and boot the platform to OS. Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297941 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13122 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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