sb/intel/i82801dx: Improve LPC device early init

Make the implementation more similar to i82801gx, enabling
ACPI PM and GPIO register spaces already in bootblock.

Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 33 insertions, 0 deletions

diff --git a/src/southbridge/intel/i82801dx/early_init.c b/src/southbridge/intel/i82801dx/early_init.c
new file mode 100644
index 0000000000..2ed7aa3f45
--- /dev/null
+++ b/src/southbridge/intel/i82801dx/early_init.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/smbus_host.h>
+#include <device/pci_ops.h>
+#include "i82801dx.h"
+
+void i82801dx_early_init(void)
+{
+	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+
+	/* Enable ACPI I/O range decode and ACPI power management. */
+	pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1);
+	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+
+	pci_write_config32(dev, GPIO_BASE, GPIOBASE_ADDR | 1);
+	pci_write_config8(dev, GPIO_CNTL, 0x10);
+
+	if (ENV_RAMINIT)
+		enable_smbus();
+}
+
+void i82801dx_lpc_setup(void)
+{
+	const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
+
+	/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
+	 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
+	 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
+	 * We also need to set the value for LPC I/F Enables Register.
+	 */
+	pci_write_config8(dev, COM_DEC, 0x10);
+	pci_write_config16(dev, LPC_EN, 0x300F);
+}