diff options
| author | david <david_wu@quantatw.com> | 2015-10-23 20:22:22 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-28 22:27:36 +0100 |
| commit | f372fb5529173817664db405055fda8895518620 (patch) | |
| tree | c3de8dc338f3b495fc7309ee2f7ba2deb9b40e82 /src/southbridge/intel/i82371eb/chip.h | |
| parent | ad038c1a14d595c88fb0b4bb6f420e4490b0a67a (diff) | |
google/lars: Add new mainboard
This is based on kunimitsu with minor changes:
- update GPIOs based on schematic
- update SPD data for memory config
- disable ALS
BUG=None
TEST=emerge-lars coreboot
Change-Id: Id1c9edfe3cc665e90683344f1662de2e65caf766
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3201aa573a77fcad3b6b1335d23eb4c2a09c1708
Original-Change-Id: Ifae446e4668569b6100b29bc1f52b0fea1df2952
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308283
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/12201
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82371eb/chip.h')
0 files changed, 0 insertions, 0 deletions