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| author | Scott Duplichan <scott@notabs.org> | 2011-02-10 20:49:56 +0000 |
|---|---|---|
| committer | Scott Duplichan <scott@notabs.org> | 2011-02-10 20:49:56 +0000 |
| commit | daecb1888ee813978a1d177a02ffd394445966a9 (patch) | |
| tree | 1c53c517567ef7d441c1b035c82ddaf5f645988f /src/southbridge/intel/i3100/pci.c | |
| parent | 20ecc5af40adbd63a3a55eefe7e53bd16412c712 (diff) | |
According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i3100/pci.c')
0 files changed, 0 insertions, 0 deletions