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| author | Aaron Durbin <adurbin@chromium.org> | 2016-11-18 08:58:25 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-19 16:56:23 +0100 |
| commit | e35e69537722bad0720a6831adc96b00d29e4a8b (patch) | |
| tree | 7e5afff0d664822f2f1857cee35bfd12c35e75e1 /src/southbridge/intel/fsp_rangeley | |
| parent | bff8c5ec1977039b7edd1de02768c44a7055fce9 (diff) | |
soc/intel/common/lpss_i2c: correct bus speed error
The wrong value was used for reporting an error when a requested
bus speed was made that isn't supported. Use the requested value.
Change-Id: I6c92ede3d95590d95a42b40422bab88ea9ae72a1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17474
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley')
0 files changed, 0 insertions, 0 deletions