aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/intel/fsp_rangeley/sata.c
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2019-06-04 13:43:25 +0200
committerNico Huber <nico.h@gmx.de>2019-10-30 21:38:03 +0000
commit63998adf4acb92e9a43533f9f82cafb28f295ac4 (patch)
treebf678157c9da72bb9626ad0190308bb540aebcd0 /src/southbridge/intel/fsp_rangeley/sata.c
parent6c2324a8f390ae05f67584e598ffd4e48e37b62f (diff)
sb/intel/common/Makefile: Use 'all' class to link files in all stages
This links the reset function, the common pmbase functions and the spi driver in all stages. The RTC code is not included in SMM as it is unused there. Change-Id: I65926046d941df3121c7483d69c0b4f7003d783e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/sata.c')
0 files changed, 0 insertions, 0 deletions