diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/intel/fsp_rangeley/lpc.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/lpc.c')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index b93bc09a62..711778e125 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -95,7 +95,7 @@ static void soc_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) +#if !CONFIG(SERIRQ_CONTINUOUS_MODE) write8(ibase + ILB_SERIRQ_CNTL, 0); #endif } @@ -435,7 +435,7 @@ static void southbridge_inject_dsdt(struct device *dev) if (gnvs) { memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); -#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) +#if CONFIG(HAVE_SMI_HANDLER) /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); #endif |