diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/intel/fsp_rangeley/early_init.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/early_init.c')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/early_init.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 844f4b8492..e4e7071cd1 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -34,15 +34,15 @@ static void rangeley_setup_bars(void) { /* Setting up Southbridge. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(LPC_BDF, RCBA, DEFAULT_RCBA | RCBA_ENABLE); + pci_write_config32(LPC_BDF, RCBA, (uintptr_t)DEFAULT_RCBA | RCBA_ENABLE); pci_write_config32(LPC_BDF, ABASE, DEFAULT_ABASE | SET_BAR_ENABLE); pci_write_config32(LPC_BDF, PBASE, DEFAULT_PBASE | SET_BAR_ENABLE); printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, "Disabling Watchdog timer..."); /* Disable the watchdog reboot and turn off the watchdog timer */ - write8(DEFAULT_PBASE + PMC_CFG, read8(DEFAULT_PBASE + PMC_CFG) | - NO_REBOOT); // disable reboot on timer trigger + write8((void *)(DEFAULT_PBASE + PMC_CFG), + read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT); // disable watchdog timer @@ -54,7 +54,7 @@ static void reset_rtc(void) { uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0; - uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1); + uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1)); int rtc_failed = !!(gen_pmcon1 & RPS); if (rtc_failed) { @@ -63,7 +63,8 @@ static void reset_rtc(void) coreboot_dmi_date); /* Clear the power failure flag */ - write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS); + write32((void *)(DEFAULT_PBASE + GEN_PMCON1), + gen_pmcon1 & ~RPS); } cmos_init(rtc_failed); |