diff options
| author | Martin Roth <gaumless@gmail.com> | 2014-05-21 14:21:22 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-07-30 19:00:44 +0200 |
| commit | 829c41da6cd9d8e9c9244c8c9ea2b181ea5ab930 (patch) | |
| tree | e4923fcc360b33e7f441031df55db731119fa508 /src/southbridge/intel/fsp_rangeley/chip.h | |
| parent | 2963ae7fd49c7086ca9c4231f00a94e2f8a33080 (diff) | |
southbridge/intel: Add fsp_rangeley support
This adds the southbridge initialization pieces for Intel's Atom C2000
processor (formerly Rangeley). It is intended to be used with the Intel
Atom C2000 FSP and does not contain all of the pieces that would
otherwise be required for initialization.
Change-Id: I416e85bd6e9c9dcf79f97785074135902fdd18b7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/6370
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/chip.h')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/chip.h | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/chip.h b/src/southbridge/intel/fsp_rangeley/chip.h new file mode 100644 index 0000000000..215454c2fe --- /dev/null +++ b/src/southbridge/intel/fsp_rangeley/chip.h @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H +#define SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H + +#include <arch/acpi.h> + +struct southbridge_intel_fsp_rangeley_config { + + /** + * GPI Routing configuration + * + * Only the lower two bits have a meaning: + * 00: No effect + * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + * 10: SCI (if corresponding GPIO_EN bit is also set) + * 11: reserved + */ + uint8_t gpi0_routing; + uint8_t gpi1_routing; + uint8_t gpi2_routing; + uint8_t gpi3_routing; + uint8_t gpi4_routing; + uint8_t gpi5_routing; + uint8_t gpi6_routing; + uint8_t gpi7_routing; + uint8_t gpi8_routing; + uint8_t gpi9_routing; + uint8_t gpi10_routing; + uint8_t gpi11_routing; + uint8_t gpi12_routing; + uint8_t gpi13_routing; + uint8_t gpi14_routing; + uint8_t gpi15_routing; + + uint32_t gpe0_en; + uint16_t alt_gp_smi_en; + + /* IDE configuration */ + uint32_t ide_legacy_combined; + uint32_t sata_ahci; + uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; + + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + + /* Override PCIe ASPM */ + uint8_t pcie_aspm_f0; + uint8_t pcie_aspm_f1; + uint8_t pcie_aspm_f2; + uint8_t pcie_aspm_f3; + uint8_t pcie_aspm_f4; + uint8_t pcie_aspm_f5; + uint8_t pcie_aspm_f6; + uint8_t pcie_aspm_f7; + + /* ACPI configuration */ + uint8_t fadt_pm_profile; + uint16_t fadt_boot_arch; + +}; + +#endif /* SOUTHBRIDGE_INTEL_RANGELEY_CHIP_H */ |