northbridge/intel/fsp_*: Remove legacy SoCs

* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
  good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
  and NORTHBRIDGE_INTEL_SANDYBRIDGE

Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 76 deletions

diff --git a/src/southbridge/intel/fsp_i89xx/bootblock.c b/src/southbridge/intel/fsp_i89xx/bootblock.c
deleted file mode 100644
index acd53dc5de..0000000000
--- a/src/southbridge/intel/fsp_i89xx/bootblock.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <cpu/x86/tsc.h>
-#include "pch.h"
-
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(void)
-{
-	u8 reg8;
-	pci_devfn_t dev;
-
-	dev = PCI_DEV(0, 0x1f, 0);
-
-	reg8 = pci_read_config8(dev, 0xdc);
-	reg8 &= ~(3 << 2);
-	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-	pci_write_config8(dev, 0xdc, reg8);
-}
-
-static void enable_port80_on_lpc(void)
-{
-	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-
-	/* Enable port 80 POST on LPC */
-	pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-	volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
-	u32 reg32 = *gcs;
-	reg32 = reg32 & ~0x04;
-	*gcs = reg32;
-}
-
-static void set_spi_speed(void)
-{
-	u32 fdod;
-	u8 ssfc;
-
-	/* Observe SPI Descriptor Component Section 0 */
-	RCBA32(0x38b0) = 0x1000;
-
-	/* Extract the Write/Erase SPI Frequency from descriptor */
-	fdod = RCBA32(0x38b4);
-	fdod >>= 24;
-	fdod &= 7;
-
-	/* Set Software Sequence frequency to match */
-	ssfc = RCBA8(0x3893);
-	ssfc &= ~7;
-	ssfc |= fdod;
-	RCBA8(0x3893) = ssfc;
-}
-
-static void bootblock_southbridge_init(void)
-{
-	enable_spi_prefetch();
-	enable_port80_on_lpc();
-	set_spi_speed();
-
-	/* Enable upper 128bytes of CMOS */
-	RCBA32(RC) = (1 << 2);
-}