diff options
| author | zaolin <zaolin.daisuki@gmail.com> | 2018-10-31 16:43:43 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-11-19 15:43:37 +0000 |
| commit | 3313a78e36da73f05da7402699f04909595a0c9d (patch) | |
| tree | 1dcd09a9df05ec94d15178f929b7ae063fdf7646 /src/southbridge/intel/fsp_i89xx/Kconfig | |
| parent | 0b8aefc6562c64665425617eddd22aec2610bda5 (diff) | |
northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_i89xx/Kconfig')
| -rw-r--r-- | src/southbridge/intel/fsp_i89xx/Kconfig | 57 |
1 files changed, 0 insertions, 57 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig deleted file mode 100644 index 0bc9586cb2..0000000000 --- a/src/southbridge/intel/fsp_i89xx/Kconfig +++ /dev/null @@ -1,57 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Google Inc. -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_INTEL_FSP_I89XX - bool - -if SOUTHBRIDGE_INTEL_FSP_I89XX - -config SOUTH_BRIDGE_OPTIONS # dummy - def_bool y - select ACPI_INTEL_HARDWARE_SLEEP_VALUES - select IOAPIC - select HAVE_SMI_HANDLER - select USE_WATCHDOG_ON_BOOT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select COMMON_FADT - select INTEL_DESCRIPTOR_MODE_CAPABLE - select NO_EARLY_BOOTBLOCK_POSTCODES - select SOUTHBRIDGE_INTEL_COMMON - select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI - -config EHCI_BAR - hex - default 0xfe700000 - - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/fsp_i89xx/bootblock.c" - -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -config HPET_MIN_TICKS - hex - default 0x80 - -endif |