Revert "Remove sandybridge and ivybridge FSP code path"

Please don't remove chipsets and mainboards without discussion and input
from the owners. Someone was asking about cougar canyon 2 just a couple
of weeks ago - there's obviously still interest.

This reverts commit fb50124d22014742b6990a95df87a7a828e891b6.

Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/12128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 59 insertions, 0 deletions

diff --git a/src/southbridge/intel/fsp_bd82x6x/watchdog.c b/src/southbridge/intel/fsp_bd82x6x/watchdog.c
new file mode 100644
index 0000000000..91bc615003
--- /dev/null
+++ b/src/southbridge/intel/fsp_bd82x6x/watchdog.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <watchdog.h>
+
+  //
+  //  Disable PCH Watchdog timer at SB_RCBA+0x3410
+  //
+  //  Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;
+  //
+void watchdog_off(void)
+{
+	device_t dev;
+	unsigned long value, base;
+
+	/* Turn off the ICH7 watchdog. */
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+
+	/* Enable I/O space. */
+	value = pci_read_config16(dev, 0x04);
+	value |= (1 << 10);
+	pci_write_config16(dev, 0x04, value);
+
+	/* Get TCO base. */
+	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+
+	/* Disable the watchdog timer. */
+	value = inw(base + 0x08);
+	value |= 1 << 11;
+	outw(value, base + 0x08);
+
+	/* Clear TCO timeout status. */
+	outw(0x0008, base + 0x04);
+	outw(0x0002, base + 0x06);
+
+	printk(BIOS_DEBUG, "PCH watchdog disabled\n");
+}