diff options
author | zaolin <zaolin.daisuki@gmail.com> | 2018-10-31 16:43:43 +0100 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2018-11-19 15:43:37 +0000 |
commit | 3313a78e36da73f05da7402699f04909595a0c9d (patch) | |
tree | 1dcd09a9df05ec94d15178f929b7ae063fdf7646 /src/southbridge/intel/fsp_bd82x6x/watchdog.c | |
parent | 0b8aefc6562c64665425617eddd22aec2610bda5 (diff) |
northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/watchdog.c')
-rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/watchdog.c | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/watchdog.c b/src/southbridge/intel/fsp_bd82x6x/watchdog.c deleted file mode 100644 index 9a867e413a..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/watchdog.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <watchdog.h> - - // - // Disable PCH Watchdog timer at SB_RCBA+0x3410 - // - // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20; - // -void watchdog_off(void) -{ - struct device *dev; - unsigned long value, base; - - /* Turn off the ICH7 watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - - /* Disable the watchdog timer. */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - - printk(BIOS_DEBUG, "PCH watchdog disabled\n"); -} |