diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:26:51 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:34:46 +0200 |
| commit | bf168e740f18da612507c14e6aebcf50d948cbf5 (patch) | |
| tree | 9cd9ee93edb42679ec896be07a0199338b083a87 /src/southbridge/intel/fsp_bd82x6x/pch.h | |
| parent | 648c9ae3715558db9dd34e414baaeabdd0028dba (diff) | |
southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I884da90d24bc41e566a290f4135166d9e0cdf474
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15682
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/pch.h')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/pch.h | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 045c2285af..7fe40f74c7 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -18,6 +18,8 @@ #ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H +#include <arch/acpi.h> + /* PCH types */ #define PCH_TYPE_CPT 0x1c /* CougarPoint */ #define PCH_TYPE_PPT 0x1e /* IvyBridge */ @@ -471,13 +473,6 @@ void display_fd_settings(void); #define GBL_EN (1 << 5) #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 #define GBL_RLS (1 << 2) #define BM_RLD (1 << 1) #define SCI_EN (1 << 0) |